1. Field of the Invention
The present invention relates generally to a semiconductor device.
2. Description of Background Art
FIG. 12A is a plan view of a conventional semiconductor device having an nMOS transistor, and FIG, 12B is a sectional view taken along line A--A of FIG. 12A. This nMOS transistor has a LDD structure and is formed in an element region of a p-type substrate 1. This element region is insulated and isolated from other elements by an element isolating insulator film 2 which is formed on the p-type substrate 1 by, e.g., the LOCOS method. A gate electrode 4 is formed on the element region via a gate insulator film 3.
On both sides of the gate electrode 4, high-density n.sup.+ -diffusion layer regions 12a, 12b serving as source and drain regions are formed. Between the n.sup.+ -diffusion layer regions 12a, 12b and a region serving as a channel arranged directly below the gate electrode 4, low-density n.sup.- -diffusion layer regions 8a, 8b are formed. The low-density and high-density diffusion layer regions and the gate electrode 4 are covered with an interlayer insulator film 17. The interlayer insulator film 17 has contact holes for providing contacts 15a, 15b to the source and drain regions 12a, 12b. Source and drain electrodes 18a, 18b are formed so as to fill in the contact holes.
FIG. 13A is a plan view of another conventional semiconductor device having an nMOS transistor, and FIG. 13B is a sectional view taken along line A--A of FIG. 13A. The nMOS transistor shown in FIGS. 13A and 13B has the same construction as that of the nMOS transistor shown in FIGS. 12A and 12B, except that high-density n.sup.+ -diffusion layer regions 12a and 12b are surrounded by low-density n.sup.- -diffusion layer regions 8a and 8b, respectively.
In such a conventional n-MOS transistor, when a surge voltage is applied to a drain electrode 18b while a source electrode 18a and a p-type substrate 1 are connected to a ground power supply, a current flows through the channel portion of the MOS transistor due to the punch through or the like, and an npn-type parasitic bipolar transistor comprising the drain region 12b, the p-type substrate 1 and the source region 12a is turned ON, so that a current flows through the parasitic bipolar transistor into the earthed power source. The current flowing by causing the parasitic bipolar transistor to be turned ON causes the avalanche breakdown phenomenon, so that a very high current flows at a stroke. This is not desired since the p-n junction between the drain-side diffusion layer region 8b or 12b and the p-type substrate 1 may be thermally broken.
In order to eliminate such a disadvantage, for example, a method for arranging a current limiting resistor 20 between a surge-voltage applied point 25 and a drain electrode 18b is used as shown in FIG. 14. The resistor 20 is made of, e.g., a polysilicon or a diffusion layer. When the resistor of the polysilicon is used, the width of the resistor must be a sufficient to prevent the resistor from being burned out by the surge current. When the resistor of the diffusion layer is used, the surge voltage is easy to cause the breakdown of the p-n junction, so that the function as a resistor may be deteriorated. Moreover, in order to prevent the function as a resistor from being deteriorated by the avalanche breakdown between a diffusion resistor (particularly a portion, to which the surge voltage is first applied) and the source of the transistor, the diffusion resistor must be isolated sufficiently from the transistor. Therefore, it is required to provide a wide area on the surface of the semiconductor substrate. That is, either case is not desired since it is required to provide a wide area for an element for coping with the ESD (Electro Static Discharge).
In place of the method for using the current limiting resistor 20, there is a method for controlling to decrease the current amplification factor of an npn-type parasitic bipolar transistor causing the avalanche breakdown so that the current value does not cause the thermal breakdown. In this method, as shown in FIGS. 15A and 15B or 16A and 16b, a source-region contact 15a is spaced from a drain-region contact 15b at a predetermined distance to decrease the current amplification factor. This is based on a model wherein a surge voltage is transmitted from a drain electrode 18b to a drain region 12b via the contact 15b to pass through the drain region 12b to a p-type substrate 1 arranged directly below the contact 15b to cause the avalanche breakdown. Furthermore, the distance between the contact 15a and the contact 15b of the n-MOS transistor shown in FIGS. 15A, 15b or 16A, 16B is greater than that of the n-MOS transistor shown in FIGS. 12A, 12B or 13A, 13B.
Thus, the surge voltage passes to the p-type substrate 1 arranged directly below the contact 15b to cause the avalanche breakdown. However, in the conventional nMOS transistor, since the sheet resistance of the n.sup.+ -diffusion layer region 12b is low, e.g., about 25 .OMEGA., the surge voltage passes to the substrate 1 even at a portion closer to the gate electrode 4 of the n.sup.+ -diffusion layer region 12b to cause the avalanche breakdown. Thus, even in the nMOS transistor having the structure shown in FIGS. 15A and 15B or 16A and 16B, the distance between the contacts must be sufficiently great to prevent the thermal breakdown from occurring. That is, the actual distance between the contacts must be greater than the distance between the contact, which is determined on the basis of the model wherein the surge voltage passes to the p-type substrate 1 arranged directly below the contact 15b to cause the avalanche breakdown. Therefore, the size of the transistor element for coping with the ESD is increased, and this is not desired.